Broadband Networks

The Internet has become a part of everyday life for many of us as a medium for information exchange and communications.  The Internet revolution began slowly with electronic mail and then skyrocketed with the advent of the World Wide Web in the early 90's.  Currently, the Internet provides mainly a data exchange service, i.e., web browsing and e-mail.  These applications alone have been enough to drive a new industry and it can be said that society has come to depend on services provided by the Internet.  But the current Internet is really only the tip of the iceberg... 

Our research is concerned with the enabling switching and networking technologies for future high performance communication networks that will provide multimedia services with quality-of-service differentiation and provisioning.  The goal of the research is to develop new architectures and algorithms to transfer information at even higher rates across future high speed networks based on fiber optic link technologies.  The broadband network architecture can be roughly subdivided into the network edge and the network core.  Basically, devices generating the network traffic, i.e., computers, LANs (local area networks), servers, etc., reside at the outermost edge of the global network.  Such devices are connected to edge switches and routers, which aggregate the traffic from the sources for delivery over the network core.  The network core consists of high speed, large capacity switches and routers that switch data transmission pipes at very high speeds. 

Another focus of our research is on high-speed network security.  We are interesting in developing network architectures and protocols that can mitigate the effects of attacks, in particular Denial-of-Service (DoS) and Distributed Denial-of-Service (DDoS) attacks, whereby the attacker (or attackers) tries to bring down the performance of a network by maliciously consuming the available network resources, thus denying network services to other users . 

For the purposes of our research, we use the term core switch to refer to a device that switches data traffic entirely in the optical domain at high speeds.  Core switches that are currently available in the market have limited switching capabilities and are based primarily on time-division multiplexing (TDM) or wavelength division multiplexing (WDM) and are essentially optical circuit switches.  Switching is performed on the time-scale of connection holding times and minimal processing is performed on the data traffic.  Devices that switch on a much faster time-scale, e.g., optical packet switches and optical burst switches are currently under active research.  We use the term edge switch to refer to a device that aggregates and processes data traffic at or near the network edge, where quality-of-service differentiation is an important issue.   

Note:  In industry usage, the terms edge and core routers have a similar distinction.  Edge routers are generally lower capacity devices owned by Internet service providers, whereas core routers are larger capacity switches typically owned by telecom carriers whose networks constitute the "network core."  In our usage, however, we go further in the distinction, generally lumping the two types of routers into the category of "edge switch" and reserving the term "core switch" to refer instead to devices that switch data traffic exclusively in the optical domain. 

Edge Switch Design

Switches or routers at the edge of the network are responsible for aggregating and switching traffic streams from communication devices located near the traffic sources.  An edge switch/router must be capable of switching a large number of traffic streams while providing quality-of-service and fairness in terms of access to the network core.  Research issues that arise in the design of edge switches/routers include:

Our recent research activities have focused on "multihop" switching fabrics that can provide scalability and growability of the switch architecture to aggregate throughputs in the Terabit regime and beyond.  In particular, we have been studying switching fabrics based on the k-ary n-cube direct network topology [LuMark02a].  Research on switch architectures in the 80's and 90's has focused mainly on what we refer to as "single-hop" switching fabrics, including output-buffered switches, input-buffered switches, input-output buffered switches, and multi-stage interconnection (MIN) based switches such as Banyan-type switches.

The k-ary n-cube interconnection structure was originally introduced and developed in the context of massively parallel computer architectures.  In recent years, some switching manufactures, notably Avici Systems, have adopted the k-ary n-cube interconnection network to build Terabit routers.  In our research, we have been studying the performance implications of the the k-ary n-cube in terms of delay and throughput characteristics [Lu02, LuMark02a].  In ongoing research, we are investigating multihop switching architectures based on a switching technique called pipelined circuit switching that are capable of providing quality-of-service. 

References:

[Lu02] X. Lu, "Modeling and Performance Evaluation of Broadband Switch Architectures," Ph.D. dissertation, Dept. of Electrical and Computer Engineering, George Mason University, Dec. 2002.

[LuMark02a] X. Lu and B.L. Mark, "Analytical Modeling of a Family of Fault-Tolerant Routing Protocols in k-ary n-cubes," Proc. Int. Symp. on Performance Evaluation of Computer and Telecommunication Systems} (SPECTS'02), pp., 900-907, San Diego, July 2002.

[Fan00] R. Fan, A. Ishii, B. Mark, T. Miura, G. Ramamurthy, Q. Ren, S. Shibuya, and K. Yamada, "ARC-LITE: An Intelligent QoS-Based
IP/ATM Edge Switch-Router,'' in Proc. XVII World Telecom.Congress/Int. Switching Symposium 2000, Birmingham, UK, May 2000.

[Fan99b] R. Fan, A. Ishii, B. Mark, G. Ramamurthy, and Q. Ren, "An Optimal Buffer Management Scheme with Dynamic Thresholds,''
in Proc. IEEE GlobeCom'99, vol. 1b, pp. 631-637, (Rio de Janeiro), November 1999.

[Fan99a] R. Fan, A. Ishii, A. Itoh, M. Kobayashi, B. Mark, T. Miura, G. Ramamurthy, Q. Ren, S. Shibuya, H. Shimonishi, and K. Yamada,
"ARC-LITE: An Integrated Quality-of-Service ATM/IP Switching-Routing Engine,'' in Proc. IEEE ATM Workshop '99, (Koichi City), pp. 161-166, May 1999.

[MFR98] B. L. Mark, R. Fan and G. Ramamurthy, "Dynamic Rate Control Scheduling for ATM Switches," in Proc. IEEE Globecom'98 , Sydney, Nov. 1998.

[Mark97] B. L. Mark, G. Ramamurthy, R. Fan, M. Shinohara, H. Suzuki, H. Iwamoto, K. Yamada, and S. Yoshikawa, "Large Capacity Multiclass ATM Core Switch Architecture," in Proc. ISS'97, Toronto, Sept. 1997.

[Shinohara97] M. Shinohara, R. Fan, B.L. Mark, G. Ramamurthy, H. Suzuki, and K. Yamada, "Multiclass Large Scale ATM Switch with QoS Guarantee,'' in Proc. IEEE ICC'97, (Montreal), June 1997.

Core Switch Design

In the network core, the main function of a core switch is to switch data traffic at extremely high speeds, with very little extraneous traffic processing.  We further assume that the switching is performed entirely in the optical domain to avoid the "electronic switching bottleneck."  Current core switches operate at the granularity of a time slot or circuit based on time-division multiplexing (TDM) technology or at the granularity of a wavelength based on wavelength-division multiplexing (WDM).  Active research is being conducted on all-optical packet switches that can switch individual packets.  The main problem faced by optical packet switches is contention resolution.  Unlike in the electronic domain, optical buffers have limited capability to resolve contention.

Our recent research has investigated the performance of new class of optical switches called optical burst switches [Lu02, LuMark03].  Optical burst switches are technologically similar to optical packet switches but instead of switching packets, they switch much large data units called bursts, which are aggregates of multiple packets.  In terms of switching granularity, optical burst switches are intermediate between optical circuit switches and optical packet switches.  Although the concept of "burst switching" is not new, the application to optical switching in the core network is promising and has generated much interest in the research community.

Our work [Lu02, LuMark03] has focused on the performance impact of fiber delay lines (FDLs) on optical burst switching.  A fiber delay line merely delays a data burst, rather than stores it in memory as in electronic buffers.  Consequently, the performance characteristics of FDLs are very different from conventional electronic buffers, which can be analyzed using conventional queueing models.  By contrast, FDLs cannot be modeled accurately using classical queueing theory.  Therefore, we have developed new performance models for FDLs in the context of optical burst switching that allow us to evaluate the performance impact of FDLs in optical contention resolution with regard to the number of FDLs and FDL length.

References:

[LuMark04] X. Lu and B.L. Mark, "Performance Modeling of Optical Burst Switching with Fiber Delay Lines," IEEE Trans. on Communications, vol. 52, no. 12, pp. 2175-2183, Dec. 2004.

[LuMark03] X. Lu and B.L. Mark, "A New Performance Model of Optical Burst Switching with Fiber Delay Lines," to appear in Proc. IEEE Int. Conf. on Comm. 2003, May 2003.

[Lu02] X. Lu, "Modeling and Performance Evaluation of Broadband Switch Architectures," Ph.D. dissertation, Dept. of Electrical and Computer Engineering, George Mason University, Dec. 2002.

[LuMark02b] X. Lu and B.L. Mark, "Analytical Modeling of Optical Burst Switching with Fiber Delay Lines,'' in Proc. IEEE/ACM MASCOTS'2002, pp. 501-506, Fort Worth, Texas, Oct. 2002.

[MarkKob95] B.L. Mark and H. Kobayashi, "Blocking in a Class of All-Optical Wavelength Routers," in Proc. 1st IEEE Int. Workshop on Broadband Switching Systems, Poznan, Poland, April 1995.

[Kob95] H. Kobayashi, B.L. Mark and Y. Osaki, "Call Blocking Probability of All-Optical Networks," in Proc. 1st IEEE Int. Workshop on Broadband Switching Systems, Poznan, Poland, April 1995.

Traffic management, routing, and congestion control

References:

[Sohn06] S. Sohn, B. L. Mark, and J. T. Brassil, "Congestion-triggered Multipath Routing based on Shortest Path Information," in Proc. Int. Conference on Computer Communications (ICCCN), Arlington, VA, Oct. 2006 (to appear).

[CMS02] F. Ciucu, B.L. Mark, and R.P. Simon, "The Partially Stopped Leaky Bucket: An Efficient Traffic Regulator with Constant Time Implementation," in Proc. Int. Symp. on Performance Evaluation of Computer and Telecommunication Systems (SPECTS'02), pp. 155-161, San Diego, July 2002.

[MarkRam98b] B.L. Mark and G. Ramamurthy, "Real-time Estimation and Dynamic Renegotiation of UPC Parameters for Arbitrary Traffic Sources in ATM Networks," IEEE/ACM Trans. on Networking, Vol. 6, No. 6, pp. 811-827, Dec. 1998.

[MarkRam98a] B.L. Mark and G. Ramamurthy, "Real-time Traffic Characterization for Quality-of-Service Control in ATM Networks," IEICE Trans. on Comm., Vol. E81-B, No. 5, pp. 832-839, May 1998.

[MJR97b] B.L. Mark, D.L. Jagerman and G. Ramamurthy, "Application of Peakedness Measures to Resource Allocation in High-Speed Networks," in Proc. 15-th Int. Teletraffic Congress, (Washington D.C.), June 1997.

[MarkRam96] B.L. Mark and G. Ramamurthy, "UPC-based traffic descriptors for ATM: How to determine, interpret and use them," Telecommunications Systems, Vol. 5, pp. 109-122, 1996. 

[MarkKob95] B.L. Mark and H. Kobayashi, "Virtual Channel and Path Allocation in ATM Networks," in Proc. IEEE Singapore Int. Conf. on Networks, Singapore, July 1995.


Last updated on July 11, 2006.